Method and system for design verification of electronic circuits

ABSTRACT

The present invention discloses an emulation system and method. The present invention comprises a control FPGA with a bi-direction interface means, a target FPGA, a microcomputer, and a data storage unit.  
     Further, the present invention further comprises an option board mounted on the motherboard through a connector.  
     Consequently, it becomes possible to implement both downloading of netlist data and monitoring of the emulation system through a single cable.

FIELD OF THE INVENTION

[0001] The present invention generally relates to software program and hardware for electronic design automation (EDA), and more particularly, to EDA tools for emulating logic circuits.

BACKGROUND OF THE INVENTION

[0002] As the semiconductor manufacturing technology advances, great deals of efforts have been made on the integration of several functional blocks in single chip.

[0003] Since today's semiconductor technology allows the system designer to integrate millions of transistors in single chip, it is crucial to design and verify electronic circuits prior to the manufacture of the prototype chip.

[0004] Thus, to verify the correctness of the circuit netlist file prior to the manufacturing, an approach known as circuit emulation is sometimes used in conjunction with EDA simulation tools.

[0005] Emulation aims to reduce or eliminate delays and costs associated with redesigning and re-manufacturing nonfunctional circuit prototypes.

[0006] Presently, various re-configurable logic devices such as field programmable gate arrays (FPGAs) are widely used for the emulation of a circuit design in conjunction with EDA tools, which enable automatic downloading of netlists.

[0007] The details of prior art circuit emulating systems are described in U.S. Pat. Nos. 5,884,066, 5,841,967, and 5,329,470.

[0008] The prior art, however, has a limitation because the conventional emulation system includes only the target FPGA where the netlists are downloaded for the configuration of the circuit design.

[0009] In addition, the prior art has further a limitation since it is inevitable to replace the whole motherboard when the current FPGA is to be upgraded in accordance with the prior art. In other words, since the signal pins on the FPGA are connected to the conducting lines on the motherboard through the dedicated pin locations on the socket, it is inevitable to replace the whole motherboard if the upgraded FPGA has a different type of pin connections.

[0010] Furthermore, the prior art has a limitation because the socket for connecting the FPGA to the motherboard becomes too expensive if the number of pins exceeds a certain number.

[0011] The soldering technology of the prior art, however, is not still recommendable because it is difficult to replace the emulation circuit board with the upgraded FPGA without damaging the motherboard.

SUMMARY OF THE INVENTION

[0012] Accordingly, it is an object of the present invention to provide a method and system for emulating a variety of circuit designs.

[0013] It is still another object of the present to provide a method and system for configuring the emulation FPGAs by downloading both the netlists and the microcomputer program simultaneously through a computer interface.

[0014] Yet it is another object of the present invention to provide a method and system for configuring the emulation FPGAs of which the control signals, the stimulus, and the microcomputer control signals are generated from the computer.

[0015] It is further an object of the present invention to provide a method and system to monitor the operation of the configured FPGAs on the computer. It is still another object of the present invention to provide a method and system for configuring the emulation FPGAs with a variety of capacity and pin types on an emulation board.

[0016] The present invention has an advantage that it is a system that can be easily upgraded to more powerful FPGAs as they become available from vendors. This allows the emulation system to be upgraded in power without changing the system's basic motherboard.

[0017] Additionally, the present invention involves a system that allows for the use of different types of FPGAs. According to the present invention, the control FPGA is configurable so as to control the microcomputer and the target FPGA.

[0018] Since the control FPGA is connected through the emulation bus on the motherboard, the target FPGAs on the option card can be upgraded or switched to different types of FPGAs without affecting the motherboard emulation bus pin locations.

[0019] The configuration data can be loaded into the target FPGAs through the control FPGAs. Furthermore, the state of the nodes in the emulation FPGAs can be monitored on the computer screen through the control FPGAs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments with the description, help explain the principles of the invention.

[0021] In the drawings:

[0022]FIG. 1 is a schematic block diagram illustrating an emulation system in accordance with a first embodiment of the present invention.

[0023]FIG. 2 is a schematic block diagram illustrating an emulation system in accordance with a second embodiment of the present invention.

[0024]FIG. 3 is a schematic diagram illustrating flow of the control signals and the state signals between the control FPGA and the target FPGA in accordance with the present invention.

[0025]FIG. 4 is a schematic diagram illustrating the operation of clock signals for the control FPGA in accordance with the present invention.

[0026]FIG. 5 is a schematic diagram illustrating an emulation system in accordance with a third embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027]FIG. 1 is a schematic block diagram illustrating an emulation system in accordance with a first embodiment of the present invention.

[0028] Referring to FIG. 1, the emulation system comprises a target FPGA 12 for the configuration of the netlists, and an interface connector 5 connecting the emulation board to the computer. The emulation system further comprises a control FPGA 4 monitoring the whole emulating process, and a microcomputer 2 monitoring the circuit verification process in terms of system level in conjunction with the emulation software.

[0029] The emulation system of the present invention further includes a memory unit 3 storing a program for the microcomputer 2 as well as the emulation data.

[0030] As a preferred embodiment in accordance with the present invention, a clock signalgenerating unit can be further comprised. Preferably, an extra memory unit for the target FPGA can further be employed.

[0031] In addition, a connector for the extension board can be used for the emulation system in accordance with the present invention. The emulation method in accordance with the present invention comprises two steps.

[0032] The first step in accordance with the present invention constitutes a downloading process of the netlists and a microcomputer program.

[0033] Thereafter, the verification whether both the target FPGA 1 and the microcomputer 2 function in a correct manner is performed. The emulation method in accordance with the present invention will be described with reference to FIG. 1.

[0034] Once the design of electronic circuit as well as a microcomputer programming is finished, the electronic circuit is transformed to an appropriate file for down loading.

[0035] Then the computer software downloads the transformed file to the control FPGA 4 on the emulation board through the downloading cable. Preferably, the netlist data is transferred to the target FPGA 1, while the microcomputer program is downloaded to a memory unit 3 under the control of the control FPGA 4.

[0036] A control circuit is configured in the control FPGA 4 in accordance with the present invention through a PROM (programmable read only memory) on the emulation board. In addition, once the computer interface circuit is configured in the control FPGA 4, a high-speed bi-directional computer interface such as EPP (enhance parallel port) or ECP (extended capabilities port) can be established.

[0037] Accordingly, the emulation system in accordance with the present invention can download the netlists and the microcomputer program very rapidly. Therefore, it becomes possible to resolve the compatibility problem in computer interface, which the prior art emulation system suffers from.

[0038] Additionally, the emulation system in accordance with the present invention configures the verification circuit through single downloading cable. Furthermore, the board control can be implemented through the same downloading cable that is also employed for the configuration of the circuits.

[0039] Referring to FIG. 1 again, among the data delivered through the computer interface bus 10, the data for the circuit verification is transferred to the target FPGA 1 through the configuration signal bus 13.

[0040] In the meanwhile, the data for the microcomputer 2 and the target FPGA 1 are stored in a data storage unit 3 through the control FPGA address bus 11 and the control FPGA data bus 12. Preferably, the emulation system can further contain a DSP (digital signal processor) chip.

[0041] In this case, the control FPGA 4 checks if the target FPGA 1 has finished the configuration of the netlist or not through the status signal. The control FPGA 4 enables the design engineer to monitor the status of the configuration of the circuit by looking at the computer screen because it sends the status signal to the computer through the computer interface.

[0042] In addition, if a multiple of target FPGAs are to be connected in a manner of daisy chain, they can be implemented through the configuration extension signal 14.

[0043] Once the preparation for the emulation is finished, the signal buses 11 and 12 are floated for the proper operation of the target FPGA 1, microcomputer 2, and a memory unit 3, while the memory address bus 15 and the memory data bus 16 are controlled by a microcomputer 12.

[0044] Preferably, the control FPGA 4 outputs the corresponding address and data, and memory control signals for storing the data in the memory unit 3 through the address bus, the control FPGA address bus 11, and the control FPGA data bus signals 12.

[0045] Now, a microcomputer 2 controls the selection of the memory unit and read/write operation. In other words, while the preparation step for the circuit verification is monitored by the control FPGA, the verification step is controlled by a microcomputer 2.

[0046] As a preferred embodiment in accordance with the present invention, the memory address bus 15 and the memory data bus 16 can be regarded as an identical signal which is connected to the control FPGA address bus 11 and the control FPGA data bus 12. There can be a variety of embodiments in terms of connecting and control schemes.

[0047]FIG. 2 is a schematic block diagram illustrating a second embodiment in accordance with the present invention. The second embodiment of the present invention has a feature of employing the microcomputer 2 for the configuration of a target FPGA.

[0048] According to a second embodiment of the present invention, the configuration data is downloaded to the control FPGA 4 through the computer interface bus 10 in such a way that the microcomputer 2 can configure the target FPGA 1 before the normal operation of the target FPGA 1.

[0049] Thereafter, the control FPGA inputs the configuration data to the memory unit 3. In this case, the microcomputer program related to the configuration of the target FPGA 1 can be also provided.

[0050] Preferably, the microcomputer program associated with the configuration of the target FPGA can be stored in a PROM connected to the microcomputer.

[0051] Once the microcomputer program associated with the configuration of the target FPGA and the configuration data are prepared, the target FPGA is configured through the microcomputer configuration bus 22.

[0052] Thereafter, the target FPGA 1 and the microcomputer become activated by the control FPGA 4 once the preparation process for the circuit verification has been completed.

[0053] As a preferred embodiment in accordance with the present invention, the stimulus applied to the emulation FPGA can be generated on the computer with computer software.

[0054] Preferably, the stimulus data can be stored in a register implemented in a control FPGA 4 through the cable, computer interface connector 5, and the computer interface bus 10.

[0055] Thereafter, the stored data is either converted to different values or applied to the target FPGA 1 through control bus 30 of the target FPGA 1 until the control is reset.

[0056] In the meanwhile, the signal status in the target FPGA can be monitored on the computer and the status signals are sent through the computer interface bus 10 by the control FPGA 4.

[0057]FIG. 3 is a schematic diagram illustrating the control signal and the operation of the status signal through the control FPGA. Referring to FIG. 3, the emulation system in accordance with the present invention, the operation of the microcomputer and the other units on the board can be monitored on the computer.

[0058] The emulation system includes a control bus 32, a status bus 33, a control bus associated with the microcomputer 34, and the status bus 35 associated with the microcomputer.

[0059] Preferably, the control FPGA in accordance with the present invention can allow the circuit designer to monitor the control or the status of an arbitrary signal through the signal connection cable 37 and pin header type connector 36 as well as the control of the predefined signals on the board.

[0060] Preferably, the change of the status signals can be stored in the storage units such as FIFO or RAMs, and then the stored data can be sent to the computer.

[0061] Since the temporal change of the status signals can be accessed and stored in the storage unit with a speed faster than the data transmission rate through the computer interface, the control signals can be applied with a very high speed when the FIFO is employed.

[0062]FIG. 4 is a schematic diagram illustrating the operation of clock signals for the control FPGA in accordance with the present invention. Referring to FIG. 4, the clock signals required for the units on the board are provided from the control FPGA.

[0063] Preferably, the circuit designer on the computer can provide the register in the control FPGA with necessary data signals such as clock frequency through the computer software.

[0064] As a preferred embodiment in accordance with the present invention, the control FPGA 4 provides the circuit modules on the board with clock signals 40 either from the external clock generating means 6 or from the internal clock.

[0065] Referring to FIG. 4 again, board clock signals 42 and microcomputer clock signals 43 from the control FPGA 4 are depicted. Preferably, the stimulus can be applied to the emulation board either by single-step or by multi-step.

[0066] As a preferred embodiment in accordance with the present invention, the stimulus can be applied through a mouse click, key-in in the table, or a waveform editor.

[0067] The response to the stimulus can be displayed on the designer's computer through the computer interface cable either in the table format or in the waveform format.

[0068] In addition, the control input can be applied either by single step or by multiple steps, and response can be monitored on the screen of the computer. As preferred embodiment in accordance with the present invention, the stimulus to the emulation FPGA can be generated in a table format with a graphic editor and the generated stimulus can be stored in a CMD file format.

[0069] In addition, the CMD file format can be converted to a table format or a waveform format. As a preferred embodiment in accordance with the present invention, the emulation system provides a probing means with TDI, TDO, TCK, TMS, and TRST associated with JTAG 1149.1 standard.

[0070] Preferably, the interface means in accordance with the present invention includes a parallel port scheme, RS232 serial interface, USB (universal serial bus) interface, IEEE 1394 interface, PCMCIA interface, and PC option card interface.

[0071]FIG. 5 is a schematic diagram illustrating an emulation system in accordance with a third embodiment of the present invention.

[0072] Referring to FIG. 5, the emulation motherboard 151, FPGA option board 152 with a connector 154, and an FPGA 153 mounted on the option board 152 are depicted.

[0073] Preferably, the emulation motherboard 151 includes a variety of display units, which allow the designer to monitor the operation of the system during emulation. As a preferred embodiment in accordance with the present invention, an additional option board can be provided for the test of the peripheral unit such as display units on the emulation motherboard 151.

[0074] The connectors on the emulation motherboard 151 and on the FPGA option board 152 are provided for interconnecting the electric signals on both boards.

[0075] The pin header of the connectors 154 in accordance with the present invention provides a testing means if the designer wants to monitor the I/O signals of the emulation FPGA with an oscilloscope.

[0076] Preferably, the pin header can be chosen as a press type. The FPGA option board 152 comprises a various kind of FPGAs, namely in terms of capacity and number of pins, in order to be compatible with the specification of the connector.

[0077] Further, various kinds of FPGAs can be employed if the printed circuit boards are modified depending on the species of the FPGA.

[0078] The control FPGA in accordance with the present invention can comprise the external data storage unit and store the status data of the selected signals in order to monitor the operation of the emulation system.

[0079] As a preferred embodiment in accordance with the present invention, the clock signals for the emulation modules on the board can be distributed under the control of the designer from the computer keyboard.

[0080] More preferably, the computer interface cable can comprise a configuring means of the emulation FPGA, a debugging means of the emulation FPGA, and a clock generating means without the control FPGA.

[0081] In addition, the computer interface cable can further comprise a downloading signal bus and a probing signal bus for verifying the emulation circuit.

[0082] According to the emulation method and system in accordance with the present invention, it becomes possible to implement a bidirectional computer interface with an excellent compatibility.

[0083] Additionally, it becomes possible to remotely control the emulation board from the designer's computer. Furthermore, it becomes possible to monitor the emulation circuit on the computer.

[0084] Since the emulation system in accordance with the present invention employs a single computer interface for downloading both the netlists and the microcomputer program, the emulation board becomes less complicated and can be remotely controlled from the keyboard.

[0085] Furthermore, since the emulation system in accordance with the present invention allows the designer to monitor the control and the status of the signals on the computer, the extra testing equipment such as an oscilloscope or a logic analyzer is not needed.

[0086] In addition, since the emulation system can be upgraded or modified just by replacing the FPGA option board from the emulation motherboard instead of replacing the whole motherboard, it becomes economical when the designer wants to upgrade the capacity of the emulation FPGAs.

[0087] Further, the emulation system in accordance with the present invention allows for the replacement of the FPGA even if some parts of board are damaged or destroyed.

[0088] It becomes also possible to monitor the status of a signal of the emulation just by probing the pin header of the PCB because the option board is mounted on the motherboard.

[0089] Although the invention has been illustrated and described with respect to exemplary embodiments thereof, it should be understood by those skilled in the art that various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention.

[0090] Therefore, the present invention should not be understood as limited to the specific embodiment set forth above but to include all possible embodiments which can be embodies within a scope encompassed and equivalents thereof with respect to the feature set forth in the appended claims. 

What is claimed is:
 1. An emulation system for emulating a circuit design comprising: a computer installed with software for emulating said circuit design; a target FPGA for configuring said circuit design; a microcomputer; a control FPGA for controlling and monitoring said target FPGA and said microcomputer; a data storage unit for storing program and data of said microcomputer; an interface through which said circuit design is downloaded; and a cable connecting said computer to said interface.
 2. The emulation system as claimed in claim 1, wherein said control FPGA receives the netlist data and said microcomputer program from said computer and stores them, thereafter enabling said target FPGA to initiate the emulation by resetting said target FPGA and said microcomputer.
 3. The emulation system as claimed in claim 1, wherein said interface comprises either one or the combination from the group of a parallel port, RS232 serial port, USB interface, IEEE 1394 interface, PCMCIA, and PC option card.
 4. The emulation system as claimed in claim 1, wherein said target FPGA is configured with the netlists of said circuit design.
 5. The emulation system as claimed in claim 1, wherein said control FPGA transfers said netlist data for configuration to said data storage unit connected to said target FPGA and let said microcomputer configure the emulation circuits by fetching said netlist data from said data storage unit.
 6. The emulation system as claimed in claim 1, wherein said control FPGA comprises FIFO internally in which the status of a selected signal of said target FPGA is stored.
 7. The emulation system as claimed in claim 1, wherein said control FPGA comprises an external data storage unit in which the status of a selected signal of said of said target FPGA is stored.
 8. The emulation system as claimed in claim 1, wherein said control FPGA distributes multiple of clock signals generated from said computer.
 9. The emulation system as claimed in claim 1, wherein said target FPGA further comprises: a display unit displaying the operation of said emulation system; a data storage unit for storing circuit operation; and a connector for an option board mounted on said emulation system.
 10. The emulation system as claimed in claim 1, wherein said emulation system further comprises a DSP unit.
 11. The emulation system as claimed in claim 1, wherein said cable comprises a means for configuring said target FPGA without said control FPGA.
 12. The emulating system as claimed in claim 1, wherein said cable comprises a debugging means for monitoring the operation of said emulation system.
 13. The emulation system as claimed in claim 1, wherein said cable comprises a clock generating means.
 14. The emulation system as claimed in claim 1, wherein said target FPGA comprises a downloading signal bus for configuring said circuit design and a probing signal bus for verifying the configured circuit.
 15. The emulation system as claimed in claim 1, wherein said control FPGA monitors and reports the command address of said microcomputer to said computer, thereby enabling the user to trace the execution of the program of said emulation software.
 16. An emulation system for emulating a circuit design comprising: a computer installed with software for emulating said circuit design; an option board including a target FPGA; a motherboard on which said option board is mounted; and a connector for mounting said option board on said motherboard.
 17. The emulation system as claimed in claim 16, wherein the number of pins between said connector and said target FPGA is different from each other.
 18. The emulation system as claimed in claim 16, wherein the pin header of said connector is protruded to a direction of said option board where said target FPGA is soldered.
 19. The emulation system as claimed in claim 16, wherein said option board comprises a header type connector for monitoring signals.
 20. A method for emulating a circuit design comprising steps of: designing a circuit on a computer installed with emulation software; downloading the netlist data to a target FPGA through a control FPGA; applying a stimulus to said target FPGA on said computer; monitoring the response to said stimulus; and displaying the response of said target FPGA on the screen of said computer.
 21. The method as claimed in claim 20, wherein said step of applying said stimulus comprises steps of: assigning a clock signal from control signals; and applying said clock signal on the computer.
 22. The method as claimed in claim 20, wherein said step of applying said stimulus comprises steps of: generating said stimulus in a table format; applying said stimulus to said target FPGA; accessing a response to said stimulus in a table format; and displaying said response on the screen of said computer.
 23. The method as claimed in claim 22, wherein said step of generating said stimulus in a table format comprises an editing step with a graphic editor on the computer.
 24. The method as claimed in claim 22, wherein said step of generating said stimulus in a table format further comprises a step of storing said stimulus in a CMD file format.
 25. The method as claimed in claim 20, wherein said emulation method further comprises steps of: storing the values of test vector in a data storage unit; applying said test vector to said target FPGA; storing the values of response vector in said data storage unit; and comparing the values of said response vector with predefined values.
 26. The method as claimed in claim 20, wherein said step of monitoring said response to said stimulus comprises a monitoring step with one or the combination from the group of TDI, TDO, TCK, TMS, and TRST of JTAG 1149.1 standard.
 27. The method as claimed in claim 24, wherein said CMD file format comprises a table format or a file format.
 28. The method as claimed in claim 20, wherein said monitoring step comprises a step of stopping the operation of said emulation system depending on the comparison with the predefined value.
 29. The method as claimed in claim 28, wherein said predefined value is set from the computer.
 30. The method as claimed in claim 28, wherein said predefined value is stored in said data storage unit on said motherboard. 